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IS62WV12816ALL IS62WV12816BLL
128K x 16 LOW VOLTAGE, ULTRA LOW POWER CMOS STATIC RAM
FEATURES
* High-speed access time: 45ns, 55ns, 70ns * CMOS low power operation - 36 mW (typical) operating - 9 W (typical) CMOS standby * TTL compatible interface levels * Single power supply - 1.65V--2.2V VDD (62WV12816ALL) - 2.5V--3.6V VDD (62WV12816BLL) * Fully static operation: no clock or refresh required * Three state outputs * Data control for upper and lower bytes * Industrial temperature available * 2CS Option Available * Lead-free available
ISSI
JUNE 2005
(R)
DESCRIPTION
The ISSI IS62WV12816ALL/ IS62WV12816BLL are highspeed, 2M bit static RAMs organized as 128K words by 16 bits. It is fabricated using ISSI's high-performance CMOS technology. This highly reliable process coupled with innovative circuit design techniques, yields highperformance and low power consumption devices. When CS1 is HIGH (deselected) or when CS2 is LOW (deselected) or when CS1 is LOW, CS2 is HIGH and both LB and UB are HIGH, the device assumes a standby mode at which the power dissipation can be reduced down with CMOS input levels. Easy memory expansion is provided by using Chip Enable and Output Enable inputs. The active LOW Write Enable (WE) controls both writing and reading of the memory. A data byte allows Upper Byte (UB) and Lower Byte (LB) access. The IS62WV12816ALL and IS62WV12816BLL are packaged in the JEDEC standard 48-pin mini BGA (6mm x 8mm) and 44-Pin TSOP (TYPE II).
FUNCTIONAL BLOCK DIAGRAM
A0-A16
DECODER
128K x 16 MEMORY ARRAY
VDD GND I/O0-I/O7 Lower Byte I/O8-I/O15 Upper Byte I/O DATA CIRCUIT
COLUMN I/O
CS2 CS1 OE WE UB LB
CONTROL CIRCUIT
Copyright (c) 2005 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774
Rev. E 06/08/05
1
IS62WV12816ALL,
PIN CONFIGURATIONS
IS62WV12816BLL
ISSI
48-Pin mini BGA (6mm x 8mm) 2 CS Option (Package Code B2)
1 2 3 4 5 6
(R)
48-Pin mini BGA (6mm x 8mm) (Package Code B)
1 2 3 4 5 6
A B C D E F G H
LB I/O8 I/O9 GND VDD I/O14 I/O15 NC
OE UB I/O10 I/O11 I/O12 I/O13 NC A8
A0 A3 A5 NC NC A14 A12 A9
A1 A4 A6 A7 A16 A15 A13 A10
A2 CSI I/O1 I/O3 I/O4 I/O5 WE A11
N/C I/O0 I/O2 VDD GND I/O6 I/O7 NC
A B C D E F G H
LB I/O8 I/O9 GND VDD I/O14 I/O15 NC
OE UB I/O10 I/O11 I/O12 I/O13 NC A8
A0 A3 A5 NC NC A14 A12 A9
A1 A4 A6 A7 A16 A15 A13 A10
A2 CS1 I/O1 I/O3 I/O4 I/O5 WE A11
CS2 I/O0 I/O2 VDD GND I/O6 I/O7 NC
44-Pin mini TSOP (Type II) (Package Code T)
PIN DESCRIPTIONS
A0-A16 I/O0-I/O15 CS1, CS2 OE WE LB UB NC VDD GND Address Inputs Data Inputs/Outputs Chip Enable Input Output Enable Input Write Enable Input Lower-byte Control (I/O0-I/O7) Upper-byte Control (I/O8-I/O15) No Connection Power Ground
A4 A3 A2 A1 A0 CS1 I/O0 I/O1 I/O2 I/O3 VDD GND I/O4 I/O5 I/O6 I/O7 WE A16 A15 A14 A13 A12
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22
44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23
A5 A6 A7 OE UB LB I/O15 I/O14 I/O13 I/O12 GND VDD I/O11 I/O10 I/O9 I/O8 NC A8 A9 A10 A11 NC
2
Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774
Rev. E 06/08/05
IS62WV12816ALL,
TRUTH TABLE
Mode Not Selected WE X X X H H H H H L L L
IS62WV12816BLL
ISSI
UB X X H X L H L L H L L I/O PIN I/O0-I/O7 I/O8-I/O15 High-Z High-Z High-Z High-Z High-Z DOUT High-Z DOUT DIN High-Z DIN High-Z High-Z High-Z High-Z High-Z High-Z DOUT DOUT High-Z DIN DIN VDD Current ISB1, ISB2 ISB1, ISB2 ISB1, ISB2 ICC ICC ICC
(R)
CS1 H X X L L L L L L L L
CS2 X L X H H H H H H H H
OE X X X H H L L L X X X
LB X X H L X L H L L H L
Output Disabled Read
Write
ICC
ABSOLUTE MAXIMUM RATINGS(1)
Symbol VTERM TSTG PT Parameter Terminal Voltage with Respect to GND Storage Temperature Power Dissipation Value -0.2 to VDD+0.3 -65 to +150 1.0 Unit V C W
Note: 1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
OPERATING RANGE (VDD)
Range Commercial Industrial Ambient Temperature 0C to +70C -40C to +85C IS62WV12816ALL 1.65V - 2.2V 1.65V - 2.2V IS62WV12816BLL 2.5V - 3.6V 2.5V - 3.6V
Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774
Rev. E 06/08/05
3
IS62WV12816ALL,
IS62WV12816BLL
ISSI
VDD 1.65-2.2V 2.5-3.6V 1.65-2.2V 2.5-3.6V 1.65-2.2V 2.5-3.6V 1.65-2.2V 2.5-3.6V Min. 1.4 2.2 -- -- 1.4 2.2 -0.2 -0.2 -1 -1 Max. -- -- 0.2 0.4 VDD + 0.2 VDD + 0.3 0.4 0.6 1 1 Unit V V V V V V V V A A
(R)
DC ELECTRICAL CHARACTERISTICS (Over Operating Range)
Symbol VOH VOL VIH VIL(1) ILI ILO Parameter Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input Leakage Output Leakage GND VIN VDD GND VOUT VDD, Outputs Disabled Test Conditions IOH = -0.1 mA IOH = -1 mA IOL = 0.1 mA IOL = 2.1 mA
Notes: 1. VIL (min.) = -1.0V for pulse width less than 10 ns.
CAPACITANCE(1)
Symbol CIN COUT Parameter Input Capacitance Input/Output Capacitance Conditions VIN = 0V VOUT = 0V Max. 8 10 Unit pF pF
Note: 1. Tested initially and after any design or process changes that may affect these parameters.
4
Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774
Rev. E 06/08/05
IS62WV12816ALL,
IS62WV12816BLL
ISSI
Max. 70 15 20 3 3 0.3 0.3 Unit mA mA mA
(R)
IS62WV12816ALL, POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range)
Symbol ICC ICC1 ISB1 Parameter VDD Dynamic Operating Supply Current Operating Supply Current TTL Standby Current (TTL Inputs) Test Conditions VDD = Max., Com. IOUT = 0 mA, f = fMAX Ind. VDD = Max., Com. IOUT = 0 mA, f = 0 Ind. VDD = Max., Com. VIN = VIH or VIL Ind. CS1 = VIH , CS2 = VIL, f = 1 MHZ OR VDD = Max., VIN = VIH or VIL CS1 = VIL, f = 0, UB = VIH, LB = VIH VDD = Max., Com. Ind. CS1 VDD - 0.2V, CS2 0.2V, VIN VDD - 0.2V, or VIN 0.2V, f = 0 OR VDD = Max., CS1 = VIL, CS2=VIH VIN 0.2V, f = 0; UB / LB = VDD - 0.2V
ULB Control ISB2 CMOS Standby Current (CMOS Inputs)
5 10
A
ULB Control
IS62WV12816BLL, POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range)
Symbol ICC Parameter VDD Dynamic Operating Supply Current Operating Supply Current TTL Standby Current (TTL Inputs) Test Conditions VDD = Max., IOUT = 0 mA, f = fMAX VDD = Max., IOUT = 0 mA, f = 0 VDD = Max., VIN = VIH or VIL CS1 = VIH , CS2 = VIL, f = 1 MHZ Com. Ind. typ.(2) Com. Ind. Com. Ind. OR Max. 45 35 40 25 3 3 0.3 0.3 Max. 55 25 30 20 3 3 0.3 0.3 Unit mA
ICC1 ISB1
mA mA
ULB Control ISB2 CMOS Standby Current (CMOS Inputs)
VDD = Max., VIN = VIH or VIL CS1 = VIL, f = 0, UB = VIH, LB = VIH VDD = Max., Com. CS1 VDD - 0.2V, Ind. CS2 0.2V, typ.(2) VIN VDD - 0.2V, or VIN 0.2V, f = 0 OR VDD = Max., CS1 = VIL, CS2=VIH VIN 0.2V, f = 0; UB / LB = VDD - 0.2V
10 10 3
10 10 3
A
ULB Control
Note: 1. At f = fMAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change. 2. Typical values are measured at VDD = 3.0V, TA = 25oC and not 100% tested.
Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774
Rev. E 06/08/05
5
IS62WV12816ALL,
AC TEST CONDITIONS
Parameter Input Pulse Level Input Rise and Fall Times Input and Output Timing and Reference Level Output Load
IS62WV12816BLL
ISSI
62WV12816BLL (Unit) 0.4V to VDD-0.3V 5ns VREF See Figures 1 and 2
(R)
62WV12816ALL (Unit) 0.4V to VDD-0.2V 5 ns VREF See Figures 1 and 2
1.65-2.2V R1() ) R2() ) VREF VTM 3070 3150 0.9V 1.8V
2.5V - 3.6V 3070 3150 1.5V 2.8V
AC TEST LOADS
R1 VTM
R1 VTM
OUTPUT 30 pF Including jig and scope R2
OUTPUT 5 pF Including jig and scope R2
Figure 1
Figure 2
6
Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774
Rev. E 06/08/05
IS62WV12816ALL,
IS62WV12816BLL
ISSI
55 ns Min. Max. 55 -- 10 -- -- -- 5 0 10 -- 0 0 -- 55 -- 55 25 20 -- 20 -- 55 20 -- 70 ns Min. Max. 70 -- 10 -- -- -- 5 0 10 -- 0 0 -- 70 -- 70 35 25 -- 25 -- 70 25 -- Unit ns ns ns ns ns ns ns ns ns ns ns ns -- 45 -- 45 20 15 -- 15 -- 45 15 --
(R)
READ CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range)
Symbol Parameter Read Cycle Time Address Access Time Output Hold Time CS1/CS2 Access Time OE Access Time
(2)
45 ns Min. Max. 45 -- 10 -- -- -- 5 0 10 -- 0 0
tRC tAA tOHA tACS1/tACS2 tDOE tHZOE tLZOE(2) tHZCS1/tHZCS2 tLZCS1/tLZCS2 tBA tHZB tLZB
(2) (2)
OE to High-Z Output OE to Low-Z Output CS1/CS2 to High-Z Output CS1/CS2 to Low-Z Output LB, UB Access Time LB, UB to High-Z Output LB, UB to Low-Z Output
Notes: 1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 0.9V, input pulse levels of 0.4 to 1.4V and output loading specified in Figure 1. 2. Tested with the load in Figure 2. Transition is measured 500 mV from steady-state voltage. Not 100% tested.
Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774
Rev. E 06/08/05
7
IS62WV12816ALL,
AC WAVEFORMS
IS62WV12816BLL
ISSI
(R)
READ CYCLE NO. 1(1,2) (Address Controlled) (CS1 = OE = VIL, CS2 = WE = VIH, UB or LB = VIL)
tRC
ADDRESS
tAA tOHA tOHA
DATA VALID
DOUT
PREVIOUS DATA VALID
AC WAVEFORMS READ CYCLE NO. 2(1,3) (CS1, CS2, OE, AND UB/LB Controlled)
tRC
ADDRESS
tAA tOHA
OE
tDOE tHZOE
CS1
tACE1/tACE2
tLZOE
CS2
tLZCE1/ tLZCE2
tHZCS1/ tHZCS2
LB, UB
tBA tLZB tHZB
DOUT
HIGH-Z
DATA VALID
Notes: 1. WE is HIGH for a Read Cycle. 2. The device is continuously selected. OE, CS1, UB, or LB = VIL. CS2=WE=VIH. 3. Address is valid prior to or coincident with CS1 LOW transition.
8
Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774
Rev. E 06/08/05
IS62WV12816ALL,
IS62WV12816BLL
ISSI
55 ns Min. Max. 55 45 45 0 0 45 40 25 0 -- 5 -- -- -- -- -- -- -- -- -- 20 -- 70 ns Min. Max. 70 60 60 0 0 60 50 30 0 -- 5 -- -- -- -- -- -- -- -- -- 20 -- Unit ns ns ns ns ns ns ns ns ns ns ns -- -- -- -- -- -- -- -- -- 20 --
(R)
WRITE CYCLE SWITCHING CHARACTERISTICS(1,2) (Over Operating Range)
Symbol Parameter Write Cycle Time 45ns Min. Max. 45 35 35 0 0 35 35 20 0 -- 5
tWC
tSCS1/tSCS2 CS1/CS2 to Write End tAW Address Setup Time to Write End tHA tSA tPWB tPWE tSD tHD tHZWE(3) tLZWE(3)
Notes:
Address Hold from Write End Address Setup Time LB, UB Valid to End of Write WE Pulse Width Data Setup to Write End Data Hold from Write End WE LOW to High-Z Output WE HIGH to Low-Z Output
1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 0.9V, input pulse levels of 0.4V to 1.4V and output loading specified in Figure 1. 2. The internal write time is defined by the overlap of CS1 LOW, CS2 HIGH and UB or LB, and WE LOW. All signals must be in valid states to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of the signal that terminates the write. 3. Tested with the load in Figure 2. Transition is measured 500 mV from steady-state voltage. Not 100% tested.
Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774
Rev. E 06/08/05
9
IS62WV12816ALL,
AC WAVEFORMS
IS62WV12816BLL
ISSI
(R)
WRITE CYCLE NO. 1(1,2) (CS1 Controlled, OE = HIGH or LOW)
tWC
ADDRESS
tSCS1 tHA
CS1
tSCS2
CS2
tAW tPWE
WE LB, UB
tSA tHZWE
tPWB
tLZWE
HIGH-Z
DOUT
DATA UNDEFINED
tSD
tHD
DIN
DATA-IN VALID
Notes: 1. WRITE is an internally generated signal asserted during an overlap of the LOW states on the CS1 , CS2 and WE inputs and at least one of the LB and UB inputs being in the LOW state. 2. WRITE = (CS1) [ (LB) = (UB) ] (WE).
10
Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774
Rev. E 06/08/05
IS62WV12816ALL,
AC WAVEFORMS
IS62WV12816BLL
ISSI
(R)
WRITE CYCLE NO. 2 (WE Controlled: OE is HIGH During Write Cycle)
tWC
ADDRESS
OE
tSCS1 tHA
CS1
tSCS2
CS2
tAW t PWE
WE
LB, UB
tSA tHZWE
HIGH-Z
tLZWE
DOUT
DATA UNDEFINED
tSD
tHD
DIN
DATA-IN VALID
Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774
Rev. E 06/08/05
11
IS62WV12816ALL,
AC WAVEFORMS
IS62WV12816BLL
ISSI
(R)
WRITE CYCLE NO. 3 (WE Controlled: OE is LOW During Write Cycle)
tWC
ADDRESS
OE
tSCS1 tHA
CS1
tSCS2
CS2
tAW tPWE
WE
LB, UB
tSA tHZWE
HIGH-Z
tLZWE
DOUT
DATA UNDEFINED
tSD
tHD
DIN
DATA-IN VALID
12
Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774
Rev. E 06/08/05
IS62WV12816ALL,
AC WAVEFORMS
IS62WV12816BLL
ISSI
t WC
ADDRESS 2
(R)
WRITE CYCLE NO. 4 (UB/LB Controlled)
t WC
ADDRESS
ADDRESS 1
OE
t SA
CS1 CS2 WE
LOW
HIGH
t HA t SA t PBW t PBW
WORD 2
t HA
UB, LB
WORD 1
t HZWE
DOUT
HIGH-Z
t LZWE t HD
DATAIN VALID
DATA UNDEFINED
t SD
DIN
t SD
DATAIN VALID
t HD
UB_CSWR4.eps
Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774
Rev. E 06/08/05
13
IS62WV12816ALL,
IS62WV12816BLL
ISSI
Min. 1.0 -- 0 Max. 3.6 10 -- -- Unit V A ns ns
(R)
DATA RETENTION SWITCHING CHARACTERISTICS
Symbol Parameter VDD for Data Retention Data Retention Current Data Retention Setup Time Recovery Time Test Condition See Data Retention Waveform VDD = 1.0V, CS1 VDD - 0.2V See Data Retention Waveform See Data Retention Waveform
VDR
IDR
tSDR tRDR
tRC
DATA RETENTION WAVEFORM (CS1 Controlled)
tSDR VDD
Data Retention Mode
tRDR
VDR CS1 VDD - 0.2V
CS1 GND
DATA RETENTION WAVEFORM (CS2 Controlled)
Data Retention Mode VDD
CS2 VDR
tSDR
tRDR
CS2 0.2V GND
14
Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774
Rev. E 06/08/05
IS62WV12816ALL,
IS62WV12816BLL
ISSI
(R)
ORDERING INFORMATION: IS62WV12816ALL (1.65V - 2.2V) Commercial Range: 0C to +70C
Speed (ns) 70 Order Part No. IS62WV12816ALL-70T Package TSOP (Type II)
Industrial Range: -40C to +85C
Speed (ns) 70 70 70 Order Part No. IS62WV12816ALL-70TI IS62WV12816ALL-70BI IS62WV12816ALL-70B2I Package TSOP (Type II) mini BGA (6mm x 8mm) mini BGA (6mm x 8mm), 2 CS Option
ORDERING INFORMATION: IS62WV12816BLL (2.5V - 3.6V) Commercial Range: 0C to +70C
Speed (ns) 45 45 55 Order Part No. IS62WV12816BLL-45B IS62WV12816BLL-45B2 IS62WV12816BLL-55T Package mini BGA (6mm x 8mm) mini BGA (6mm x 8mm), 2 CS Option TSOP (Type II)
Industrial Range: -40C to +85C
Speed (ns) 55 55 55 55 55 Order Part No. IS62WV12816BLL-55TI IS62WV12816BLL-55TLI IS62WV12816BLL-55BI IS62WV12816BLL-55BLI IS62WV12816BLL-55B2I Package TSOP (Type II) TSOP (Type II), Lead-free mini BGA (6mm x 8mm) mini BGA (6mm x 8mm), Lead-free mini BGA (6mm x 8mm), 2 CS Option
Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774
Rev. E 06/08/05
15
PACKAGING INFORMATION
Mini Ball Grid Array Package Code: B (48-pin)
Top View 1 2 3 4 56 6
ISSI
Bottom View
b (48x)
(R)
5
4
3
2
1
A B C D D E F G H D1
e
A B C D E F G H
e E E1
A2 SEATING PLANE A1
A
Notes: 1. Controlling dimensions are in millimeters.
mBGA - 6mm x 8mm
MILLIMETERS Sym.
N0. Leads A A1 A2 D D1 E E1 e b -- 0.24 0.60 7.90 5.90
mBGA - 8mm x 10mm
INCHES Min. Typ. Max. Sym.
N0. Leads
MILLIMETER Min. Typ. Max.
48 -- 0.24 0.60 9.90 7.90 -- -- -- -- -- 1.20 0.30 -- 10.10 8.10 --
INCHES Min. Typ. Max.
Min. Typ. Max.
48 -- -- -- -- -- 1.20 0.30 -- 8.10 6.10
-- 0.009 0.024 0.311 0.232
-- -- -- -- --
0.047 0.012 -- 0.319 0.240
A A1 A2 D D1 E E1 e b
-- -- -- -- --
0.047 0.012 -- 0.398 0.319
0.009 0.024 0.390 0.311
5.25 BSC 3.75 BSC 0.75 BSC 0.30 0.35 0.40
0.207 BSC 0.148 BSC 0.030 BSC 0.012 0.014 0.016
5.25 BSC 3.75 BSC 0.75 BSC 0.30 0.35 0.40
0.207 BSC 0.148 BSC 0.030 BSC 0.012 0.014 0.016
Copyright (c) 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774
Rev. D 01/15/03
PACKAGING INFORMATION
Plastic TSOP Package Code: T (Type II)
ISSI
Notes: 1. Controlling dimension: millimieters, unless otherwise specified. 2. BSC = Basic lead spacing between centers. 3. Dimensions D and E1 do not include mold flash protrusions and should be measured from the bottom of the package. 4. Formed leads shall be planar with respect to one another within 0.004 inches at the seating plane.
(R)
N
N/2+1
E1
E
1 D
N/2
SEATING PLANE
ZD
A
.
e b L A1 C
Symbol Ref. Std. No. Leads A A1 b C D E1 E e L ZD
Millimeters Min Max
Inches Min Max
Plastic TSOP (T - Type II) Millimeters Inches Min Max Min Max 44 -- 1.20 -- 0.047 0.05 0.15 0.002 0.006 0.30 0.45 0.012 0.018 0.12 0.21 0.005 0.008 18.31 18.52 0.721 0.729 10.03 10.29 0.395 0.405 11.56 11.96 0.455 0.471 0.80 BSC 0.032 BSC 0.41 0.60 0.016 0.024 0.81 REF 0.032 REF 0 5 0 5
Millimeters Min Max 50 -- 1.20 0.05 0.15 0.30 0.45 0.12 0.21 20.82 21.08 10.03 10.29 11.56 11.96 0.80 BSC 0.40 0.60 0.88 REF 0 5
Inches Min Max
(N) 32 -- 1.20 -- 0.047 0.05 0.15 0.002 0.006 0.30 0.52 0.012 0.020 0.12 0.21 0.005 0.008 20.82 21.08 0.820 0.830 10.03 10.29 0.391 0.400 11.56 11.96 0.451 0.466 1.27 BSC 0.050 BSC 0.40 0.60 0.016 0.024 0.95 REF 0.037 REF 0 5 0 5
-- 0.047 0.002 0.006 0.012 0.018 0.005 0.008 0.820 0.830 0.395 0.405 0.455 0.471 0.031 BSC 0.016 0.024 0.035 REF 0 5
Copyright (c) 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. -- www.issi.com -- 1-800-379-4774
Rev. F 06/18/03

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